Building of VHDL Reusable Components for DSP- oriented Architectures

In recent years, the hardware description languages, and the standard VHDL in particular, are intensively used to describe different aspects of hardware designs. The rapid development of CAD tools on the language basis have sped up and improved the design process considerably. The design methods, however, have not kept the pace with the needs and requirements for design productivity and quality. The main reason of this is a steady increase of the complexity of electronic systems and the need to decrease the time to market. The system complexity, for example, rose around 50% in 1995, whereas the design productivity was left behind with 21% increase. It is predicted that growing of the so-called “productivity gap” will remain for the future [Lehmann et al., 1996]. Consequently, alternative design methods must be found to further reduce of the development time and increase the design quality.